The present application claims priority to Japanese Application No. P10-275925 filed Sep. 29, 1998 which application is incorporated herein by reference to the extent permitted by law.
1. Field of the Invention
The present invention relates to a packaged semiconductor device comprised of a semiconductor chip mounted while preventing a reduction of characteristics and to a method of production of the same.
Further, the present invention relates to a method for mounting a semiconductor chip or filter chip or other component on a substrate, more particularly relates to a method of mounting preferred for mounting a semiconductor chip or component for high speed, high frequency applications.
2. Description of the Related Art
In recent years, advances in cellular telephones, integrated service digital networks (ISDNs), personal computers (PC), and other information communication (network) technologies have led to attempts to mount high frequency communication blocks, high speed serial interfaces, etc. in a variety of apparatuses.
When mounting such a high speed, high frequency circuit block in an apparatus, it is necessary to assemble this circuit block at low cost and compactly. In addition, a method of mounting taking in account high speed operation, reduction of noise, etc. has been demanded.
Due to such demands, attention has been paid to multi-chip modules, (MCM) flip-chip mounting, and other bare chip mounting technologies as methods for mounting semiconductor chips.
In flip-chip mounting, usually a projecting electrode (bump) is formed on each of the input-output (I/O) pads of the semiconductor chip and the semiconductor chip is turned faced down and connected to a substrate by solder or the like. For this reason, flip-chip mounting has the characteristic features that the wiring paths are formed shorter compared with a case of connection using wire-bonding or the like, a low inductance, a low capacitance, and a low resistance can be realized, operation is high in speed, and the high frequency characteristics are excellent.
FIG. 18 shows an example of the configuration in the case where a semiconductor chip is mounted on a mother board by the flip-chip technology.
In order to achieve this mounting structure 100, high melting point solder bumps 104 are formed in advance on the I/O pads of the semiconductor chip 102. Further, solder 108 is precoated at predetermined positions on interconnection patterns 106a on the mother board 106.
In this state, the semiconductor chip 102 is turned face down and positioned onto the mother board 106. The two are then connected by applying heat and pressure.
Next, a connection portion of the semiconductor chip 102 and the mother board 106 is filled with a resin 110 so as to relieve the thermal stress applied to the soldered portions, to protect the surface of the semiconductor chip 104, or due to other demands for reliability.
Summarizing the problems to be solved by the invention, in this flip-chip connection method, however, the interconnections on the semiconductor chip 102 are further covered by an organic substance (resin 110) other than a protective layer 102a at the surface. As a result, an increase of a parasitic capacitance component or other change of impedance occurs.
Particularly, in the case of microwave monolithic integrated circuits (MMIC), some high speed digital ICs, and the like where the interconnections are formed by microstrip lines, coplanar lines, or the like, this change in the impedance detracts from the impedance matching and other optimum design conditions and results in the various characteristics being lowered from their design values.
Further, changes occur in the constants of spiral inductors or other passive elements and, in addition, the characteristics are degraded due to a dielectric loss.
Further, the addition of the organic substance on to the top part of field effect transistors (FET) causes an increase of a gate capacitance and becomes a cause of a reduction of the noise factor.
This change in impedance causes serious changes in the characteristics in surface acoustic wave (SAW) filters and other filters based on a vibration mode of a surface acoustic wave.
On the other hand, particularly in the case of a high frequency semiconductor circuit, usually it is necessary to metalize the back of the semiconductor chip 102 and to sufficiently stably ground this back surface metal. This is because, in for example MMICs, the interconnections are frequently formed by using microstrip lines or coplanar (grounded coplanar) lines.
In the flip-chip mounting structure as shown in FIG. 18, however, there is the disadvantage that the back surface metal cannot be sufficiently stably reduced to the ground potential.
Further, particularly in ICs comprised of high power circuits etc., the heat generation is also large. It many cases, a structure where the chip back surface is connected to the mother board via a conductive layer by die bonding as in the related art becomes necessary.
In the flip-chip mounting structure shown in FIG. 18, however, when mounting an IC having high power circuits, air cooling from the chip back side alone is not sufficient for dissipation of the heat. As a result, there is a strong apprehension of a reduction of the output power of the IC or other reductions in characteristics.
For this reason, in particular for mounting a semiconductor chip for high speed, high frequency applications or where a high output power is required, the conventional mounting method, that is, the method of die-bonding the semiconductor chip with its element forming surface facing upward, connecting the terminals by wire bonding, then performing a complex sealing step in a nitrogen atmosphere for accommodating the chip in a hollow package, has been adopted.
Accordingly, due to the complicated process, the need for expensive and large size packages of ceramic and metal, and the high cost of this mounting method, a small size and low cost mounting method for high speed, high frequency applications or high power usages has been strongly demanded.
An object of the present invention is to provide a packaged semiconductor device having high characteristics and reliability and low cost.
Another object of the present invention is to provide a method of mounting a semiconductor chip or other component which enables a small parasitic inductance etc. and facilitates heat dissipation and ground while using flip-chip mounting and which results in excellent characteristics and reliability and low cost.
According to a first aspect of the present invention, there is provided a semiconductor device comprising a package board having interconnection patterns on one main surface, a semiconductor chip electrically connected through internal terminations to interconnection patterns of the package board and having an element forming surface facing the package board across a space, and a conductive plate connected to a back surface of the semiconductor chip of a side opposite to the element forming surface through a conductive bonding layer, the semiconductor chip being sealed in a resin formed in a circumferential direction in the space between the package board and the conductive plate.
Preferably, the one main surface of the package board is provided with a depression enlarging the space in the thickness direction of the package board.
Preferably, the device further comprises external terminations formed on the other main surface of the package board and electrically connected to corresponding interconnection patterns and connectors formed in the resin and electrically connecting the conductive plate to the interconnection patterns electrically connected to external terminations for supply of a reference potential.
More preferably, the element forming surface of the semiconductor chip is formed with a circuit, electrode pads for an input signal or an output signal of the circuit are provided at opposite two sides among the four sides of the semiconductor chip, and the connectors are arranged at the outside of the other two sides of the semiconductor chip.
Preferably, the other main surface of the package board is formed with external terminations electrically connected to corresponding interconnection patterns, the element forming surface of the semiconductor chip is formed with a circuit, and external terminations for an input signal or an output signal are arranged below electrode pads for an input signal or output signal of the circuit.
Preferably, the resin is mainly comprised of an epoxy-based resin, an acryl-based resin, or an acid anhydride-based resin alone or in mixtures of two or more types, is formed into a gel or paste by addition of a curing agent, and is shrunken by a heat reaction.
According to a second aspect of the present invention, there is provided a method of production of a semiconductor device comprising a step of forming a package board having interconnection patterns on one main surface, a step of forming internal terminations on an element forming surface of a wafer for forming a semiconductor chip or the interconnection patterns, a step of securing the semiconductor chip to the package board so as to make it be electrically connected through the internal terminations to the interconnection patterns and so that the element forming surface faces the package board across a space, a step of making a conductive plate be connected to a back surface of the semiconductor chip through a conductive bonding layer, and a step of securing the package board and the conductive plate at a peripheral part of the semiconductor chip by a resin so that the space is maintained at the element forming surface side of the semiconductor chip.
Preferably, the step of forming the package board includes a step of forming a depression enlarging the space in the thickness direction of the package board at a location where one main surface of the package board will face the element forming surface of the semiconductor chip.
Preferably, the method further comprises a step of forming on the other main surface of the package board external terminations for electrical connection with corresponding interconnection patterns and a step of forming connectors on the interconnection patterns electrically connected to external terminations for supply of a reference potential, the conductive plate contacting and being electrically connected to the connectors in the step of connection of the conductive plate, the resin being supplied around the connectors in the step of securing by the resin.
Preferably, the step of connection of the conductive plate includes a step of supplying a conductive bonding layer to a predetermined position of a back of the semiconductor chip, a step of positioning a conductive plate on the back of the semiconductor chip and mounting it while applying pressure and heat, and a step of cooling while maintaining the pressure at the time of applying the above pressure as it is.
Preferably, the resin includes dispersed therein ceramic particles.
According to a third aspect of the present invention, there is provided a method of production of a semiconductor device comprising a step of forming a package board having interconnection patterns on one main surface, a step of forming internal terminations on an element forming surface of a wafer for forming a semiconductor chip or the interconnection patterns, a step of securing a semiconductor chip on a conductive plate so that the back surface at a side opposite to the element forming surface is electrically connected through a conductive bonding layer, a step of supplying a resin around a chip securing location of the package board, and a step of securing the conductive plate to which the semiconductor chip is secured to the package board so that the semiconductor chip is electrically connected through the internal terminations to the interconnection patterns, the element forming surface of the semiconductor chip faces the package board across a space, and the semiconductor chip is sealed by the resin.
Preferably, the method further comprises a step of forming bumps on electrode pads of the semiconductor chip as the internal terminations, wherein the step of securing the conductive plate comprises a step of supplying a conductive layer on to the interconnection patterns, a step of positioning so that the bumps come over the conductive layer and mounting the conductive plate to which the semiconductor chip is secured on to the package board while applying pressure and heat, and a step of cooling while maintaining the pressure at the time of applying the above pressure as it is.
Preferably, the method further comprises a step of forming on the other main surface of the package board external terminations for electrical connection to the corresponding interconnection patterns and a step of placing connectors on the resin, in the step of securing the conductive plate, the connectors being buried in the resin in a state of electrical connection between the interconnection patterns electrically connected to an external connection for supply of a reference potential and the conductive plate.
Preferably, the resin is processed into a tape form for supply on the package board.
Preferably, the resin contains dispersed therein conductive particles.
Preferably, the conductive particles are comprised of metal balls or of plastic balls coated with a metal.
According to a fourth aspect of the present invention, there is provided a method of mounting a component for face-down mounting of a component formed with elements on its surface from an element forming surface to a mounting board, the method of mounting a component comprising a step of forming a depression at a location of the mounting board, having interconnection patterns at one main surface, where the component is to be mounted and a step of bringing the element forming surface into alignment with the location where the depression was formed and securing the component to the mounting board.
Preferably, the method further comprises a step of securing a conductive plate to a surface of the component at a side opposite to the element forming surface while electrically connecting it to interconnection patterns of the mounting board for supply of a reference potential.
In the semiconductor device according to the present invention and the methods of production of the same or the method of mounting a component according to the present invention, the semiconductor chip, surface elastic filter, or other component is mounted face-down onto a mounting board or package board across a space. Accordingly, the resin or other organic substance does not contact the element-forming surface of the component in the mounting step and therefore the impedance etc. of the component does not change from the design values.
Further, particularly, in the semiconductor device, since corresponding external terminations are provided below signal input use or signal output use electrode pads of the semiconductor chip, the distance from the semiconductor chip to the external terminations can be made shortest.
Further, since one direction of the component (back surface in the case of a semiconductor chip) is electrically connected to the board via a conductive plate, a grounding route and a heat dissipation route by a conductive material are reliably secured.
Due to the above, mounting becomes possible while keeping reduction of the characteristics of the components as low as possible.
Particularly, in the semiconductor device, since the resin is formed at the peripheral part of the sides so as not to cause a reduction of the characteristics of the semiconductor chip and the semiconductor chip is sealed by the resin, the hermeticity is high and intrusion of moisture and contaminants from the outside is effectively prevented.
Among the methods of production of the semiconductor device, in the method supplying the resin before connecting the semiconductor chip to the package board, the connectors for connecting the conductive plate to the interconnection patterns for the supply of the common potential of the package board are embedded after the supply of the resin, but if conductive particles are contained in the resin, conductivity will be manifested by application of pressure. Therefore, electrical connection of the two is achieved due to the application of pressure when embedding the connectors in the resin even if the connectors do not contact the interconnection patterns.